sidewall (Total 5428 Patents Found)

Apparatus for printing on frusto-conical cups includes a mandrel wheel intermittently rotatably movable to a loading, pre-treatment, printing, first cure, second cure, and unloading station; a plurality of mandrel assemblies rotatably mounted on the mandrel wheel for holding the containers on the mandrel wheel; a stati...
A method of manufacturing a semiconductor device having a submicron pattern. A p-type semiconductor layer is formed on an n-type semiconductor substrate. Insulating films are formed on the p-type semiconductor layer. A first mask layer, such as an aluminum layer having an etching rate different from that of the insulat...
A molding apparatus and process is described in which a side wall mold insert is accessible and releasable from the interior of the molding apparatus. A fastener reversibly seats the side wall insert to the mold frame, the insert having an inclined rim wall for engaging a complementary-shaped wall of an adjacent tread ...
Each of an elevated diode sensor optoelectronic product and a method for fabricating the elevated diode sensor optoelectronic product employs a sidewall passivation dielectric layer passivating a sidewall of a patterned conductor layer which serves as a bottom electrode for an elevated diode within the elevated diode s...
Provided are semiconductor devices that may include a substrate provided with a transistor, an insulating layer disposed on the substrate, the insulating layer including a contact hole exposing a portion of the transistor, a spacer disposed on an inner sidewall of the contact hole, and a contact plug disposed in the co...
The invention utilizes introductions of oxygen and hydroxyl to perform an in situ steam generated (ISSG) process to anneal and reoxidize a conventional sidewall oxide layer in a shallow trench isolation. The ISSG annealing process renders the conventional sidewall oxide layer much less stress. The electrical property o...
There is disclosed herein a transistor having a sidewall base contact. The base region of the transistor is in a column of selectively grown epitaxial silicon isolated from adjacent structures in a field of oxide. The sidewall base contact is a layer of doped polysilicon which is embedded in the insulating material sur...
An integrated circuit fabrication process and transistor is provided in which salicidation is virtually eliminated from the spacer sidewall surface. Absent salicidation on that surface, bridging effects cannot occur regardless of the anneal conditions. The spacer sidewall surfaces is made substantially perpendicular to...
A semiconductor device includes a metal gate stack. The metal gate stack includes a high-k gate dielectric and a metal gate electrode over the high-k gate dielectric. The metal gate electrode includes a first top surface and a second bottom surface substantially diametrically opposite the first top surface. The first t...
An improved series and/or parallel connection of transistors within a logic gate is presented. The improved connection is brought about by a sacrificial structure on which gate conductors are formed adjacent sidewall surfaces of the sacrificial structure. The sacrificial structure thereby provides spacing between the s...
A magnetic tunnel junction device comprises a substrate including a patterned wiring layer. A magnetic tunnel junction (MTJ) stack is formed over the wiring layer. A low-conductivity layer is formed over the MTJ stack and a conductive hard mask is formed thereon. A spacer material is then deposited that includes a diff...
The invention is a multilayer tire sidewall having an outer layer prepared from a blend of isomonoolefin/para-alkylstyrene copolymer and general purpose rubbers. The inner layer comprises general purpose rubber. The resulting sidewall exhibit good ozone resistance and fatigue crack resistance as well as a reduction in ...
An improved source/drain junction configuration in a metal-oxide semiconductor transistor is provided, as well as a novel method for fabricating this junction. This configuration employs gate double sidewall spacers in the peripheral region and gate single sidewall spacers in the cell array region. The double sidewall ...
The present invention provides a method of forming a metal seed layer 100 . The method includes physical vapor deposition of seed metal 200 within an opening 140 located in a dielectric layer 135 of a substrate 110 . The method also includes a RF plasma etch of the seed metal 200 deposited in the opening 140...
Spacer structures are formed around an array of disposable mandrel structures and above a doped semiconductor material portion. A sidewall image transfer process is employed to pattern an upper portion of the doped semiconductor material portion into an array of doped semiconductor fins. After formation of a dielectric...
This invention discloses a through-silicon via (TSV) structure for providing an electrical path between a first-side surface and a second-side surface of a silicon chip, and a method for fabricating the structure. In one embodiment, the TSV structure comprises a via penetrated through the chip from the first-side surfa...
A structure of a capacitor includes two gates and a commonly used source/drain region on a substrate. Then, a pitted self align contact window (PSACW) partly exposes the commonly used source/drain region. Then an glue/barrier layer and a lower electrode of the capacitor are over the PSACW. Then a dielectric thin film w...
A method for forming a patterned silicon containing layer. There is first provided a substrate. There is then formed over the substrate a blanket silicon containing layer. There is then formed over the blanket silicon containing layer a patterned photoresist layer. There is then etched, while employing a first plasma e...
A semiconductor structure with electrically isolated sidewall electrodes on one or more sides of the structure and a method for fabricating the structure are disclosed. The electrically isolated sidewall electrodes are composed of silicon-based conductive material, e.g., doped polysilicon, which allows the electrodes t...
The present disclosure generally relates to forming a metallization layer in a semiconductor device. In particular, this disclosure concerns the damascene inlay technique in low-k dielectric layers. Etching trenches and vias in low-k dielectric materials leads to uneven and porous sidewalls of the trenches and vias due...
A method used to fabricate a semiconductor device comprises etching a dielectric which results in an undesirable charge buildup along a sidewall formed in the dielectric during the etch. The charge buildup along a top and a bottom of the sidewall can reduce the etch rate thereby resulting in excessive etch times and un...
A method for making DRAM cells with minimum active device areas (cell areas) using novel sidewall-spacer bit lines is achieved. A trench is etched in an insulating layer aligned over the device areas and orthogonal to the gate electrodes, and extending over the first and second source/drain areas. A conducting layer is...
Improved film spacers for the sidewalls within semiconductor structures are disclosed. The spacers are made of non-conformal, organic materials, such as polyimides, acrylates, methacrylates, and various photoresist compositions. They are formed on the sidewalls by a process which involves the formation of overhang stru...
A gate structure ( 30 ) is formed over a semiconductor ( 10 ). Sidewall structures ( 200 ) of a first width W 1 are formed adjacent to the gate structure ( 30 ) and source and drain regions ( 90 ) are formed in the semiconductor ( 10 ). An etch process is performed to reduce the width of the sidewall structure to W 2 ...
An etchant including C 2 H x F y , where x is an integer from two to five, inclusive, where y is an integer from one to four, inclusive, and where x plus y equals six, etches doped silicon dioxide with selectivity over both undoped silicon dioxide and silicon nitride. Thus, undoped silicon dioxide and silicon nitride m...
The present invention relates to an FET device having a conductive gate electrode with angled sidewalls. Specifically, the sidewalls of the FET device are offset from the vertical direction by an offset angle that is greater than about 0° and not more than about 45°. In such a manner, such conductive gate electrode h...
An non-volatile read only memory transistor for use in a memory array is disclosed. The non-volatile read only memory transistor features a substantially vertically oriented channel fabricated in a trench formed in the substrate. The channel length is dependent upon the depth of the trench and therefore a dense array o...
Provided is a method for removing barrier layer for minimizing sidewall recess. The method comprises the following steps: introduce noble-gas-halogen compound gas and carrier gas into an etching chamber within which a thermal gas phase etching process is being performed for etching a barrier layer (206) on non-recessed...
The invention provides a rubber composition for the sidewall of a fire fighting truck. The rubber composition is composed of, by weight, 65-115 parts of base body rubber, 20-40 parts of carbon black, 12-22 parts of fire retardant, 3-5 parts of antiager, 2-9 parts of resin, 2-6 parts of active agents, 1-3 parts of vulca...
(57)【要約】 【課題】単一側壁構造のリール本体を持つ改良されたス ピニングリールを提供すること。 【解決手段】前方開口部(5、105又は205)又は 後方開口部(305)とこの開口部に着脱可能な蓋板 (13、113、21...
This invention relates to tires which have a rubber insert within the tire sidewall of a rubber composition which contains at least one of N,N'-(m-phenylene) bis citraconamic acid and N,N'-(m-xylylene) bis citraconamic acid. Such rubber insert is preferably of a stiff rubber composition which helps to support t...
A method for fabricating a semiconductor apparatus includes forming a variable resistor region, and forming a spacer having a top linewidth and a bottom linewidth substantially equal to each other in the variable resistor region. The forming of the spacer includes forming a first insulating layer in the variable resist...
Preprinted rectangular blanks of longitudinally stretch-oriented foam sheet material are formed into cylinders by a continuous folder and seamer and transferred onto mandrels on which they are shrunken by heat to assume the shape of the mandrel. In forming containers, means are provided to place bottom blanks on the ma...
A FET device comprising a semiconductor substrate; diffusion regions in the substrate separated by a channel region; a gate overlapping the channel region and a portion of the diffusion regions and separated from the substrate by a gate dielectric; and a sidewall dielectric on a sidewall of the gate; and a sidewall spa...